XR28V384IM48-0A-EB Datasheet, PDF (23/42 Pages) Exar Corporation – XR28V384 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
Bits [7:0]: LSB of UART base address (0x61)
The default value of this register is determined by the strapping options. See Table 1 ’UART Power On
Configuration’.
2.1.2.1.3
IRQ Channel Select Register - Read/Write
The V384 supports different IRQ channels and modes. The IRQ modes and IRQ channel number for each
device of V384 should be programmed in their respective IRQ Channel Selelct register. Each device of V384
can have same/different IRQ channel.
Bits [3:0]: Select the IRQ channel
The default values of these bits is determined by the strapping options See Table 1 ’UART Power On
Configuration’. They can also be configured via software after power on.
Bit [4]: Enable/Disable the IRQ Sharing mode
x Logic 0 = Disable the IRQ sharing mode (default). The IRQ channel must be different for each UART for
proper behavior.
x Logic 1 = Enable the IRQ sharing mode. The IRQ channel (bits 3-0) can be different or be the same as the
other UARTs.
Bits [6:5]: IRQ Sharing mode
These two bits are effective only when IRQ sharing mode is enabled (bit[4] = ’1’). The SERIRQ time slot is
specified by bits 3-0. An interrupt will only appear on the SERIRQ pin during that time slot if MCR[3] = ’1’.
x ’00’ = The IRQ Sharing mode is active LOW level (default). There will be an active low pulse continuously on
the SERIRQ pin until the interrupt has been cleared.
x ’01’ = The IRQ Sharing mode is active LOW edge. When there is an interrupt, there will be a single active low
pulse on the SERIRQ pin.
x ’10’ = The IRQ Sharing mode is active HIGH level. There will be an active high pulse continuously on the
SERIRQ pin until the interrupt has been cleared.
x ’11’ = Reserved.
Bit [7]: Reserved
2.1.2.1.4
Enhanced Multifunction Register - Read/Write
This register enables/disables the RS-485 mode, 9-bit mode, selects clock frequency and delay in the IR
mode.
23