XR17V252_08 Datasheet, PDF (26/69 Pages) Exar Corporation – 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
3.1.1 Normal Rx FIFO Data Unloading at locations 0x100 (channel 0) and 0x300 (channel 1)
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0) and 0x300 (channel 1). This operation is
at least 16 times faster than reading the data in 64 separate 8-bit memory reads of RHR register (0x000 for
channel 0 and 0x200 for channel 1).
READ RX FIFO,
WITH NO ERRORS
Read n+0 to n+3
Read n+4 to n+7
Etc.
BYTE 3
FIFO Data n+3
FIFO Data n+7
BYTE 2
FIFO Data n+2
FIFO Data n+6
BYTE 1
FIFO Data n+1
FIFO Data n+5
BYTE 0
FIFO Data n+0
FIFO Data n+4
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0300
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
3.1.2 Special Rx FIFO Data Unloading at locations 0x180 (channel 0) and 0x380 (channel 1)
The XR17D152 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0) and 0x380 (channel 1). The entire RX data along with the status can be
downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be
read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
READ RX FIFO,
WITH LSR ERRORS
Read n+0 to n+1
Read n+2 to n+3
Etc
BYTE 3
FIFO Data n+1
FIFO Data n+3
BYTE 2
LSR n+1
LSR n+3
BYTE 1
FIFO Data n+0
FIFO Data n+2
BYTE 0
LSR n+0
LSR n+2
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
the Configuration Register Address 0x0180 and 0x0380
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
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