XR17V252_08 Datasheet, PDF (16/69 Pages) Exar Corporation – 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
Registers INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. Bit [10:8] represent channel 0 and channel 1 with bits [13:11]. The 3 bit encoding and their priority
order are shown below in Table 8. The Timer and MPIO interrupts are for the device and therefore they exist
within channel 0 (bits [10:8]) only..
FIGURE 5. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
INT2 Register
INT1 Register
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Channel-1
Channel-0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N
INT0 Register
Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
TABLE 8: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING
PRIORITY BIT[N+2] BIT[N+1]
x
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
BIT[N]
0
1
0
1
0
1
0
1
INTERRUPT SOURCE(S)
None or wake-up indicator
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only in channel 0, reserved in channel 1.
TIMER Time-out. Available only in channel 0, reserved channel 1.
TABLE 9: UART CHANNEL [1:0] INTERRUPT CLEARING
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
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