XR17V252_08 Datasheet, PDF (15/69 Pages) Exar Corporation – 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT

REV. 1.0.2
XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
TABLE 7: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
0x080-083
0x084-087
0x088-08B
0x08C-08F
0x090-093
REGISTER
INTERRUPT (read-only)
TIMER (read/write)
ANCILLARY1 (read/write)
ANCILLARY2 (read-only)
MPIO (read/write)
BYTE 3 [31:24] BYTE 2 [23:16] BYTE 1 [15:8] BYTE 0 [7:0]
INT3
INT2[
INT1
INT0
TIMERMSB
TIMERLSB TIMER (reserved) TIMERCNTL
SLEEP
RESET
REGA
8XMODE
MPIOINT
REGB
DVID
DREV
MPIOSEL
MPIOINV
MPIO3T
MPIOLVL
1.6.1 The Global Interrupt Register
The XR17V252 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme uses bits 0 to 1 of an 8-bit indicator (INT0) representing
channels 0 to 1 of the XR17V252, respectively. This permits the interrupt routine to quickly vector and serve
that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt
status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service.
INT0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code per channel. This 3-bit code represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 6-bit interrupt
status for both channels. Bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1.
Bits 14 to 31 are reserved and remain at logic zero. Both channels interrupt status are available with a single
DWORD read operation. This feature allows the host to quickly vector and serve the interrupts, reducing
service interval, hence, reducing host bandwidth requirements. Figure 5 shows the 4-byte interrupt register
and its make up.
GLOBAL INTERRUPT REGISTER (DWORD) [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
A special interrupt condition is generated by the V252 when it wakes up from sleep mode. This special
interrupt is cleared by reading the INT0 register. If there are not any other interrupts pending, the value read
from INT0 would be 0x00.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-1
indicates channel 1. Logic 1 indicates that a channel has requested for service. Bits 2 to 7 are reserved and
remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
The INT0 register provides status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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