XR21V1412_10 Datasheet, PDF (25/30 Pages) Exar Corporation – 2-CH FULL-SPEED USB UART

XR21V1412
REV. 1.1.0
2-CH FULL-SPEED USB UART
3.4.2 LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
• Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
• Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
3.4.3 CUSTOM_INT_PACKET (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 26 and Table 18, “Data Field of Customized Interrupt Packet -
Exar Vendor Specific,” on page 27.
CUSTOM_INT_PACKET[0]: GPIO1
• Logic 0 = Disable GPIO1 status in custom interrupt packet.
• Logic 1 = Enable GPIO1 status in custom interrupt packet.
CUSTOM_INT_PACKET[1]: GPIO2
• Logic 0 = Disable GPIO2 status in custom interrupt packet.
• Logic 1 = Enable GPIO2 status in custom interrupt packet.
CUSTOM_INT_PACKET[2]: Reserved
• This bit is reserved and should remain ’0’.
CUSTOM_INT_PACKET[3]: GPIO0
• Logic 0 = Disable GPIO0 status in custom interrupt packet.
• Logic 1 = Enable GPIO0 status in custom interrupt packet.
CUSTOM_INT_PACKET[4]: GPIO3
• Logic 0 = Disable GPIO3 status in custom interrupt packet.
• Logic 1 = Enable GPIO3 status in custom interrupt packet.
CUSTOM_INT_PACKET[5]: GPIO4
• Logic 0 = Disable GPIO4 status in custom interrupt packet.
• Logic 1 = Enable GPIO4 status in custom interrupt packet.
CUSTOM_INT_PACKET[6]: GPIO5
• Logic 0 = Disable GPIO5 status in custom interrupt packet.
• Logic 1 = Enable GPIO5 status in custom interrupt packet.
CUSTOM_INT_PACKET[7]: Reserved
This bit is reserved and should remain ’0’.
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