XR16L2551 Datasheet, PDF (25/48 Pages) Exar Corporation – LOW VOLTAGE DUART WITH POWERSAVE

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REV. 1.0.0
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
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