XR17D154 Datasheet, PDF (24/69 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
xr
REV. 1.2.0
4.0 TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel in the device configuration register
set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it
increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data
byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register
(LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates
data unloading with the error flags without having to read the LSR register separately. Furthermore, the
XR17D154 supports PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
4.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS
The XR17D154 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the 16550 register set) where the RX and the TX FIFO can be read from/written to, as
shown in Table 3 on page 13. The following is an extract from the table showing the burstable memory
locations:
Channel 0:
RX FIFO
:
0x100 - 0x13F (64 bytes)
TX FIFO
:
0x100 - 0x13F (64 bytes)
RX FIFO + status
:
0x180 - 0x1FF (64 bytes data + 64 bytes status)
Channel 1:
RX FIFO
:
0x300 - 0x33F (64 bytes)
TX FIFO
:
0x300 - 0x33F (64 bytes)
RX FIFO + status
:
0x380 - 0x3FF (64 bytes data + 64 bytes status)
Channel 2:
RX FIFO
:
0x500 - 0x53F (64 bytes)
TX FIFO
:
0x500 - 0x53F (64 bytes)
RX FIFO + status
:
0x580 - 0x5FF (64 bytes data + 64 bytes status)
Channel 3:
RX FIFO
:
0x700 - 0x73F (64 bytes)
TX FIFO
:
0x700 - 0x73F (64 bytes)
RX FIFO + status
:
0x780 - 0x7FF (64 bytes data + 64 bytes status)
4.1.1 Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
and 0x700 (channel 3). This operation is at least 16 times faster than reading the data in 64 separate 8-bit
memory reads of RHR register (0x000 for channel 0, 0x200 for channel 1, 0x400 for channel 2, and 0x600 for
channel 3).
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