XR17D154 Datasheet, PDF (21/69 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART

xr
REV. 1.2.0
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
2.2.10 MPIO REGISTER
Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and
monitor the 8 multipurpose inputs and outputs pins. Figure 8 shows the internal circuitry.
FIGURE 8. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
MPIOINT [7:0]
IN T
AND
Rising Edge
D e te ctio n
AND
1
MPIOLVL [7:0]
Read Input Level
0
M P IO
Pin [7:0]
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIO3T [7:0]
(3-state Enable =1)
OR
MPIOSEL [7:0]
(Select Input=1, Output=0 )
M P IO C KT
MPIOINT [7:0] - (default 0x00)
Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit-0 enables input pin
0 for interrupt, and bit-7 enables input pin 7. No interrupt is enable if the pin is selected to be an output. The
interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after
a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active
low or active high, it’s level trigger. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it.
M PIOINT Register
Multipurpose Input/Output Interrupt Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
21