XR17D154 Datasheet, PDF (12/69 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
TABLE 2: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
xr
REV. 1.2.0
ADDRESS BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
15:0
RWR^{1 Subsystem Vendor ID (write from external EEPROM by cus-}
tomer)
0x0000
0x30 31:0
RO Expansion ROM Base Address (Unimplemented)
0x00000000
0x34 31:0
RO Reserved (returns zeros)
0x00000000
0x38 31:0
RO Reserved (returns zeros)
0x00000000
0x3C 31:24
RO Unimplemented MAXLAT
0x00
23:16
RO Unimplemented MINGNT
0x00
15:8
RO Interrupt Pin, use INTA#.
0x01
7:0
RWR Interrupt Line.
0xXX
NOTE: RWR¹=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
2.2 Device configuration Register Set
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the D154 UART and for monitoring the status of various functions. The registers occupy 2K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset
control, and device identification and revision, and others.
The registers set is mapped into 4 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error flags.
12