XRP9710 Datasheet, PDF (23/36 Pages) Exar Corporation – Dual 6A Programmable Power Module

XRP9710 and XRP9711
Dual 6A Programmable Power Module
LDOS
The XRP9710/1 has an internal Low Drop-Out
(LDO) linear regulator that generates 5.0V
(LDO5) for both internal and external use.
LDO5 is the main power input to the device
and is supplied by an external 5.5V to 25V V_CC
supply. The 5V output is used by the
XRP9710/1 as a standby power supply and
supply power to the 5V gate drivers. The total
output current that the 5V LDO can provide is
130mA.
The XRP9710/1 consumes
approximately 20mA and the rest is the gate
drive currents. During initial power up, the
maximum external load should be limited to
30mA.
For operation with a V_CC of 4.75V to 5.5V, the
LDO5 output needs to be connected directly to
V_CC on the board.
CLOCKS AND TIMING
÷4/÷8
Reg
Clock
Divider
Ext Clock Output
GPIO1
Ext Clock Input
GPIO0
PLL
x4/x8
Reg
System Clock
Frequency
Set Reg
DPWM
Base Frequency
2x
4x
Sequencer
Freg Mult Reg
SEL
CH1 Timing
To Channels 2→4
Figure 24 XRP9710 Timing Block Diagram
Figure 24 shows a simplified block diagram of
the XRP9710/1 timing. Again, please note
that the function blocks and signal names
used are chosen for ease of understanding
and do not necessarily reflect the actual
design.
The system timing is generated by a 103MHz
internal system clock (Sys_Clk). There are
two ways that the 103MHz system clock can
be generated. These include an internal
oscillator and a Phase Locked Loop (PLL) that
is synchronized to an external clock input.
The basic timing architecture is to divide the
Sys_Clk down to create a fundamental
switching frequency (Fsw_Fund) for all the
output channels that is settable from 124kHz
to 306kHz. The switching frequency for a
channel (Fsw_CHx) can then be selected as 1
time, 2 times or 4 times the fundamental
switching frequency.
To set the base frequency for the output
channels, an “Fsw_Set” value representing
the base frequency shown in Table 1, is
entered into the switching frequency
configuration register. Note that Fsw_Set
value is basically equal to the Sys_Clk divided
by the base frequency. The system timing is
then created by dividing down Sys_Clk to
produce a base frequency clock, 2X and 4X
times the base frequency clocks, and
sequencing timing to position the output
channels relative to each other. Each output
channel then has its own frequency multiplier
register that is used to select its final output
switching frequency.
Table 1 shows the available channel switching
frequencies for the XRP9710/1 device. The
shaded areas show the allowable frequencies
of the internal power stages. In practice the
PowerArchitect™ 5.1 (PA 5.1) design tool
© 2014 Exar Corporation
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Rev. 1.0.1