XR17V354 Datasheet, PDF (18/66 Pages) Exar Corporation – HIGH PERFORMANCE QUAD PCI-EXPRESS UART

XR17V354
PRELIMINARY
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. P1.0.2
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [3] indicates channel 3. The upper four bits INT0[7:4] are reserved. Logic 1 indicates the channel N [3:0] has
called for service. The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
The INT0 register provides individual status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
0 0 0 0 Bit-3 Bit-2 Bit-1 Bit-0
INT3, INT2 and INT1 [31:8] 3-bit Channel Interrupt Encoding
Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bits [10:8] represent channel 0
and go up to channel 3 with bits [19:17]. The 3-bit encoding and their priority order are shown below in Table 7.
The wake-up interrupt, timer/counter interrupt and MPIO interrupt are only reported in channel 0 of INT1
(bits[10:8]). These interrupts are not reported in any other location.
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
INT2 Register
INT1 Register
Reserved
0
0
0
Reserved
Reserved
0
0
00
0
0
Reserved
0
0
0
Channel-3
Channel-2
Channel-1
Channel-0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
N+2 N+1 N N+2 N+1 N N+2 N+1 N N+2 N+1 N
INT0 Register
Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
0
0
0
0 Bit-3 Bit-2 Bit-1 Bit-0
TABLE 7: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING
PRIORITY BIT[N+2] BIT[N+1]
x
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
BIT[N]
0
1
0
1
0
1
0
1
INTERRUPT SOURCE(S)
None or wake-up indicator (wake-up indicator is reported in channel 0 only)
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Reported in channel 0 only.
Timer/Counter. Reported in channel 0 only.
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