XR17V354 Datasheet, PDF (13/66 Pages) Exar Corporation – HIGH PERFORMANCE QUAD PCI-EXPRESS UART

REV. P1.0.2
PRELIMINARY
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
0xB0 31:0
RO PCIe Capability Offset 0x30 - Link Status2/Control2
0x00010001
0xB4-0xFF 31:0
RO Not implemented or not applicable (return zeros)
0x00000000
0x100 31:0
RO VC Resource Capability Register
0x00010002
0x104- 31:0
0x113
RO Not implemented or not applicable (return zeros)
0x00000000
0x114 31:0
RO VC Offset 0x4
0x8000000FF
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
1.2 EEPROM Interface
The V354 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
EEPROM must be organized into address/data pairs. The first word of the pair is the address and the second
word is the data. Table 2 below shows the format of the 16-bit address:
TABLE 2: EEPROM ADDRESS BIT DEFINITIONS
BIT(S)
DEFINITION
15
Parity Bit - Odd parity over entire address/data pair
If there is a parity error, it will be reported in bit-3 of the REGB register in
the Device Configuration Registers (offset 0x08E).
14
Final Address
If 1, this will be the last data to be read.
If 0, there will be more data to be read after this.
13:8
Reserved - Bits must be ’0’
7:0
Target Address - See Table 3
13