XR17V358 Datasheet, PDF (15/68 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL PCI EXPRESS UART

PRELIMINARY
XR17V358
REV. P1.0.2
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
1.3 Device Internal Register Sets
The Device Configuration Registers and the eight individual UART Configuration Registers of the V358
occupy 8K of PCI bus memory address space. These addresses are offset onto the basic memory address, a
value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The
UART Configuration Registers are mapped into 8 address blocks where each UART channel occupies 1024
bytes memory space for its own registers that include the 16550 compatible registers. The Device
Configuration Registers are accessible from all UART channels. However, not all bits can be controlled by all
channels. The UART channel can only control the 8XMODE, 4XMODE, RESET and SLEEP register bits that
apply to that particular channel. For example, this prevents channel 0 from accidentally resetting channel 1.
All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address given by the
host at the beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32
bits format in special locations given in the Table 4 below. Every time a read or write operation is made to the
transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location
either in byte, word or DWORD. One special case applies to the receive data unloading when reading the
receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to
maintain integrity of the data byte with its associated error flags. These special registers are further discussed
in “Section 2.1, FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT” on page 31.
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