XR17V358 Datasheet, PDF (13/68 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL PCI EXPRESS UART

REV. P1.0.2
ADDRESS
OFFSET
BITS
0x7C 31:0
0x80 31:16
15:8
7:0
0x84 31:16
15:8
7:0
0x88 31:16
15:8
7:0
0x8C 31:24
23:22
21:18
17:15
14:12
11:10
9:4
3:0
0x90 31:21
20
19
18
17:15
14:10
9:4
3:0
0x94 31:0
0x98-0xAF 31:0
0xB0 31:0
0xB4-0xFF 31:0
0x100 31:0
PRELIMINARY
XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
RO No soft reset when transitioning from D3hot to D0 state
0x00000008
RO PCI Express 2.0 capable endpoint, Interrupt Message Number 1
0x0202
RO Next Capability Pointer
0x00
RO PCI Express Capability ID
0x10
RO Not implemented or not applicable (return zeros)
0x0000
RO Role-Based Error Reporting
0x80
RO 256 bytes max payload size
0x01
RW Not implemented or not applicable (return zeros)
0x0000
RW 512 bytes max read request, Enable No Snoop
0x28
RW 256 bytes max TLP payload size
0x10
RO Port Number
0x01
RO Not implemented or not applicable (return zeros)
00b
RO Not implemented or not applicable (return zeros)
0000b
RO L1 Exit Latency < 1 us
000b
RO L0s Exit Latency < 64 ns
000b
RO Active State Power Management (ASPM) Support
11b
L0s and L1 Supported
RO x1 max Link Width
000001b
RO 2.5GT/s Link speed supported
0001b
RO Not implemented or not applicable (return zeros)
00000000000b
RO Data Link Layer Active Reporting capable
1b
RO Surprise Down Error Reporting not supported
0b
RO Reference clock must not be removed.
0b
RO L1 Exit Latency - 2 us to less than 4 us
010b
RO Not implemented or not applicable (return zeros)
00000b
RO x1 negotiated Link Width
000001b
RO Current Link Speed is 2.5GT/s
0001b
RO PCIe Capability Offset 0x14 - Slot Capabilities Register
0x00040000
RO Not implemented or not applicable (return zeros)
0x00000000
RO PCIe Capability Offset 0x30 - Link Status2/Control2
0x00010001
RO Not implemented or not applicable (return zeros)
0x00000000
RO VC Resource Capability Register
0x00010002
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