XR17V358 Datasheet, PDF (1/68 Pages) Exar Corporation – HIGH PERFORMANCE OCTAL PCI EXPRESS UART

PRELIMINARY
XR17V358
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
JULY 2009
REV. P1.0.2
GENERAL DESCRIPTION
The XR17V358¹ (V358) is a single chip 8-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V358 serves as a
single lane PCIe bridge to 8 indepedent enhanced
16550 compatible UARTs. The V358 is compliant to
PCIe 2.0 Gen 1 (2.5GT/s).
In addition to the UART channels, the V358 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V358 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
25Mbps. The V358 is available in a 176-pin FPBGA
package (13 x 13 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
• Next generation Point-of-Sale Systems
• Remote Access Servers
• Storage Network Management
• Factory Automation and Process Control
• Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
• Single 3.3V power supply
• Internal buck regulator for 1.2V core
• PCIe 2.0 Gen 1 compliant
• x1 Link, dual simplex, 2.5Gbps in each direction
• Expansion bus interface
• EEPROM interface for configuration
• Data read/write burst operation
• Global interrupt status register for all eight UARTs
• Up to 25 Mbps serial data rate
• 16 multi-purpose inputs/outputs (MPIOs)
• 16-bit general purpose timer/counter
• Sleep mode with wake-up Indicator
• Eight independent UART channels controlled with
■ 16550 compatible register Set
■ 256-byte TX and RX FIFOs
■ Programmable TX and RX Trigger Levels
■ TX/RX FIFO Level Counters
■ Fractional baud rate generator
■ Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■ Automatic Xon/Xoff software flow control
■ RS-485 half duplex direction control output
with programmable turn-around delay
■ Multi-drop with Auto Address Detection
■ Infrared (IrDA 1.1) data encoder/decoder
• Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
FIGURE 1. BLOCK DIAGRAM OF THE XR17V358
TX+
TX-
RX+
RX-
CLK+
CLK-
CLKREQ#
PERST#
EN485#
E N IR #
EECK
EEDI
EEDO
EECS
D [7:0]
SEL
CLK
IN T
MODE
PRES
C o n fig u ratio n
Space
R eg isters
PInCtPIeCLr _foIaeccael
Bus
In te rfa c e
C o n fig u ratio n
E_RE_eSP_gpiR^ascO_{t ee}M_{r s}
In te rfa c e
E xp an sio n
In te rfac e
B uck R egulator
125 M H z C lo ck
G lobal
C onfiguration
R egisters
16- b it
T im er/C o u n ter
UART Channel 0
UART
Regs
26546- - b y t e T X F IF O
TTXX && RR XX
IR
ENDEC
B R G 26546- - bbyyttee RRXX FFIIFFOO
UART Channel 1
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
UART Channel 6
UART Channel 7
MMuullttii-- p u r p o s e
In p u ts/O u tp u ts
C rystal O sc/B uffer
TT XX [[ 77 :: 00 ]]
R X [7:0]
RRTTSS##[[77::00]]
DDTTRR##[[77::00]]
C T S #[7:0]
D S R #[7:0]
D C D #[7:0]
R I#[7:0]
M MP IPOIO[ 1[57::00]]
TM RCK
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