ZSSC1856 Datasheet, PDF (98/179 Pages) List of Unclassifed Manufacturers – Intelligent Battery Sensor IC

ZSSC1856
Intelligent Battery Sensor IC
4.2.2 Flash Memory
There is a 96 KB flash memory integrated into the system to store the boot loader, the program code, and logging
data. As the flash memory has some dedicated timings for the control signals when erasing (part of) the flash and
when writing data to the flash, a flash controller is used for flash integration into the system to support all
mandatory operations (read, write, erase) to be performed on the different flash locations and to guarantee the
correct timings for write and erase operations. It is also checked whether the different operations are allowed to be
performed depending on the memory protection scheme.
The flash memory consists of two sections: the MAIN area and the INFO pages. Together these sections
comprise several pages of 512 bytes each. Each page has four rows, and each row contains 32 words. A flash
page is the smallest block that can be erased.
The INFO pages have a total size of 1 KB while the size of the MAIN area is 96 KB. Each word is protected by
ECC logic with a hamming distance of 4, which enables the system to correct a single-bit error and to detect two-
bit errors within a word. The correct ECC code bits are automatically appended on each write access to the flash.
When a single-bit error within a word is detected during a read access, it is automatically corrected.
The occurrence of bit errors is signaled via dedicated status bits in registers FC_STAT_DATA (see Table 4.18)
and FC_STAT_PROG (see Table 4.17) in the flash controller. The status bits distinguish between an erased flash
word (all1 flag), the detection and correction of a single-bit error (1Err flag), and the detection of more than one bit
error (2Err flag), which is uncorrectable.
The two status register sets are distinguished by the type of flash access:
 FC_STAT_PROG status bits are used when errors occur during an instruction fetch.
o An instruction fetch to an erased memory location (all1 flag set) or to a memory location with
more than one error (not correctable!) will assert a NMI as the program is corrupted.
o The detection and correction of a single-bit error within a word is signaled via the normal interrupt
(ARM^® interrupt line 0).
 FC_STAT_DATA status bits are used when errors occur during a load operation.
o Loads from an erased memory location as well as the detection (and correction) of errors within a
word are indicated via the normal interrupt (ARM^® interrupt line 0).
Figure 4.1 Flash Memory Example: BOOT Section of 7 Flash Pages (3.5kB) and
PROG Section of 22 Flash Pages (11kB)
LOG
0x03A00
Programmed logStart Address:
0x1D (0x03A00 >> 9)
PROG
0x0
INFO
BOOT
MAIN
0x00E00
0x00000
Programmed progStart Address:
0x07 (0x00E00 >> 9)
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev.1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
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