ZSSC1856 Datasheet, PDF (166/179 Pages) List of Unclassifed Manufacturers – Intelligent Battery Sensor IC

ZSSC1856
Intelligent Battery Sensor IC
Transmission:
A transmission is started by writing the data to be transmitted into the TX buffer (write to Z2_USARTDATA). As
this register is only 8-bit wide, the ninth bit (MSB) in mode 3 must be written to TxBit8 (Z2_USARTCFG[7]) before
writing the LSBs to the TX buffer. Writing to the TX buffer clears the status flag “TxBufEmpty” in the status register
Z2_USARTSTAT. When the transmitter is idle (bit “TxSrEmpty” is 1), the START bit and the STOP bit are added
to the TX data and all 10/11 bits are moved into the TX shift register. The status flag “TxBufEmpty” is cleared, and
the data is shifted out of the module. Both the START bit and the STOP bit have a length of 1 bit. New data can
be written into “TxBit8” and into the TX buffer when the buffer is marked as empty (directly after the data transfer
into TX shift register).
When the data is shifted out and further data is present in the TX buffer, the next transfer follows immediately.
When no further data is present, the transmitter stops and the “TxSrEmpty” flag is set. When the software tries to
write to the TX buffer or to change TxBit8 while the buffer is not empty (bit “TxBufEmpty” is 0), the write access is
rejected (old data is kept) and the write collision flag “WrColl” is set.
All three flags (“TxSrEmpty”, “TxBufEmpty”, “WrColl”) are allowed to drive the interrupt line when they are enabled
for this via register Z2_USARTIRQEN. All three flags are set to their default values when the module is disabled.
The flag “TxSrEmpty” is also set and cleared by hardware only. The flag “TxBufEmpty” is set by data transfer into
the shift register and cleared by write access to the TX buffer. “WrColl” is only set by hardware and cleared on read
access to the status register Z2_USARTSTAT.
Reception:
The module synchronizes to incoming data on the falling edge on the RXD line (START detection). After half a
period, it is checked if the value on the RXD line is still 0. If this is not the case, the actual transfer is stopped, the
status flag “StartErr” is set and the module waits on the next falling edge on the RXD line. This error condition can
occur due to a mismatch in the programmed period in both devices, due to a spike on the RXD line which caused
the erroneous synchronization or due to a misaligned enable of the module. The last situation could be avoided by
software, if both devices send 0xFF as data for an initial synchronization. In this case, only the START bit would
drive the data line low. The flag “StartErr” is set by hardware and is cleared by read access to the status register
Z2_USARTSTAT or when module is disabled. Further data reception is not blocked when this bit is set. When
enabled via Z2_USARTIRQEN, this flag is allowed to drive the interrupt line.
When operating in mode 2 and the “Mpce” bit (Z2_USARTCFG[4]) is 0, the received data byte is stored into the
RX buffer and the level of the received STOP bit is stored into RxBit8 (Z2_USARTSTAT[7]). The data is stored at
the sampling position of the STOP bit. If the “Mpce” bit is 1 instead, the received byte and STOP bit are only
stored when the STOP bit has a value of 1. Otherwise the data is rejected. The rejection is not signaled to the
software.
When data is stored in the RX buffer, the “RxFull” flag is set. This flag is cleared by reading the data out of the RX
buffer. If the RX buffer is marked as full when new data is received, the new data is rejected and the “RxOf” status
flag is set. As there is no overflow check for “RxBit8,” the status including “RxBit8” must be read before the RX
buffer.
The flag “RxOf” is set by hardware and cleared by read access to the status register or when the module is
disabled. When enabled via register Z2_USARTIRQEN, this flag is allowed to drive the interrupt line. Also the
“RxFull” flag is set by hardware and is allowed to drive the interrupt line. This flag is cleared on read access to the
RX buffer, but it is not cleared when module is disabled to avoid loss of data.
When operating in mode 3, 9 instead of 8 data bits are received. The module behaves almost the same, except
that there is no check for the STOP bit level. Instead the level of the ninth data bit can be checked when bit
“Mpce” is set to 1. This can be used for multiprocessor communication.
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev.1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
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