ZSSC1856 Datasheet, PDF (140/179 Pages) List of Unclassifed Manufacturers – Intelligent Battery Sensor IC

ZSSC1856
Intelligent Battery Sensor IC
When a new byte is written into the TX buffer before the end of an active byte transfer, the transfer of the new
byte starts immediately after the actual transfer. This means that the busy flag stays active at the end of the first
transmitted byte.
As it can be possible that the software disables the SPI while a transfer is in progress (not recommended), a byte
could be present in the TX buffer indicated by a low value of the TxEmpty flag. This byte can be removed from the
TX buffer by writing a 1 to the ClrTxBuf bit of the status register as it would be transmitted when SPI is enabled
again.
As mentioned above, the user can configure the SPI clock frequency by the CDIV field. The SPI clock frequency
is
SPI clock frequency = system clock frequency / (2 * (CDIV + 1))
Figure 4.12 SPI Bus and Status Flags for a Single Byte Transfer
byte boundary
SCLK (POL == 0; PHA == 0)
SCLK (POL == 1; PHA == 0)
SCLK (POL == 0; PHA == 1)
SCLK (POL == 1; PHA == 1)
MOSI
MSB
MISO
MSB
busy
txEmpty
rxFull
LSB
LSB
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev.1.00
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.
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