ZSSC1856 Datasheet, PDF (109/179 Pages) List of Unclassifed Manufacturers – Intelligent Battery Sensor IC

ZSSC1856
Intelligent Battery Sensor IC
4.3.5 SMU Module Register Overview
4.3.5.1 Register “SYS_CLKCFG” – Clock Configuration
Table 4.5
Name
clkDiv
unused
enSclk2
unused
Register “SYS_CLKCFG” – system address 0x4000_0000
Bits
[1:0]
[6:2]
Default
0
0
Access
RW
RO
Description
Clock divider value
0: incoming clock is divided by 1
1: incoming clock is divided by 2
2: incoming clock is divided by 4
3: incoming clock is divided by 8
Unused; always write as 0.
[7]
0
[31:8] 0
RW Enable bit for ZSYSTEM2 clock
RO Unused; always write as 0.
4.3.5.2 Register “SYS_MEMPORTCFG” – Memory and Port Configuration
Table 4.6 Register “SYS_MEMPORTCFG” – system address 0x4000_0004
Name
ppNod
spiCfg
usartCfg
i2cCfg
unused
linTest
memSwap
Bits
[15:0]
[17:16]
[20:18]
[23:21]
[29:24]
[30]
[31]
Default
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
RO
RW
RW
Description
Output configuration bits.
It can be individually selected for each GPIO whether it will
work as an open-drain (set to 0) or as a push-pull (set to 1).
Configuration bits for SPI in ZSYSTEM2.
[0]: enable connection between GPIOs and SPI
[1]: select 1 of 2 port sets to which SPI will be mapped
Configuration bits for USART in ZSYSTEM2.
[0]: enable connection between GPIOs and USART
[2:1]: select 1 of 4 port sets to which USART will be mapped.
Important: The RXD line is always open-drain; settings from
ppNod are overridden.
Configuration bits for I²C in ZSYSTEM2.
[0]: enable connection between the GPIOs and I²C
[2:1]: select 1 of 4 port sets to which I²C will be mapped.
Important: both I²C lines are always open-drain; settings from
ppNod are overridden.
Unused; always read as 0.
Configuration bit for LIN test. When set, RXD and TXD line are
directly connected to GPIO.
Memory swap bit.
It can be selected whether the flash MAIN area (set to 0) or the
RAM (set to 1) shall be mirrored to system address 0x0.
Data Sheet
April 24, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev.1.00
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