SGU01G64A1BG1SA-BBR Datasheet, PDF (9/16 Pages) List of Unclassifed Manufacturers – 1024MB DDR3 . SDRAM UDIMM

Data Sheet
Rev.1.1 11.04.2013
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE, ≤ + 85°C°, VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time CL = 11
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
Read CMD to 1^st data
CK high-level width
CK low-level width
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS
SYMBOL
t_CK (11)
t_CK (10)
t_CK (9)
t_CK (8)
t_CK (7)
t_CK (6)
t_CK (5)
t_AA
t_CH
t_CL
t_HZ
t_LZ
t_DS(Base)
12800-CL11
MIN MAX
1.25
1.5
1.5 <1.875
1.5 <1.875
1.875 <2.5
1.875 <2.5
2.5
3.3
3.0
3.3
13.75
-
0.47 0.53
0.47 0.53
-
225
-450 225
-
-
DQ and DM input hold time
relative to DQS
t_DH(Base)
-
-
DQ and DM input setup time
relative to DQS VREF=1V/ns
t_DS1V
160
-
DQ and DM input hold time
relative to DQS VREF=1V/ns
t_DH1V
145
-
DQ and DM input pulse width
( for each input )
t_DIPW
360
-
DQS, DQS# to DQ skew, per
access
t_DQSQ
-
100
DQ-DQS hold, DQS to first DQ t_QH
to go non-valid, per access
0.38
-
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
CK#
t_DQSH
t_DQSL
t_DQSCK
0.45
0.45
-225
0.55
0.55
225
DQS, DQS# rising to/from CK,
CK# when DLL disabled
DQS falling edge to CK rising
- setup time
t_DQSCK
DLL_DIS
t_DSS
1
10
0.18
-
DQS falling edge from CK rising t_DSH
- hold time
0.18
-
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
t_RPRE
t_RPST
t_WPRE
t_WPST
t_DQSS
0.9
0.3
0.9
0.3
- 0.27
Note1
Note2
-
-
+ 0.27
Address and control input pulse t_IPW
width ( for each input )
560
-
CTRL, CMD, Addr setup to CK, t_IS(Base)
CK#
45
-
CTRL, CMD, Addr setup to CK, t_IS(1V)
CK#
VREF @ 1V/ns
220
-
1 The maximum preamble is bound by tLZDQS (MAX)
2 The maximum postamble is bound by tHZDQS (MAX)
10600-CL9
8500-CL7
MIN MAX
MIN
MAX Unit
-
-
-
-
1.5 <1.875
-
-
1.5 <1.875
-
-
1.875 <2.5
1.875 <2.5
-
1.875
-
<2.5 ^ns
2.5
3.3
2.5
3.3
3.0
3.3
3.0
3.3
13.5
-
13.125
-
0.47 0.53 0.47
0.53 tCK
0.47 0.53 0.47
0.53 tCK
-
0.25
-
0.3 ns
-0.5 0.25
-0.6
0.3 ns
30
-
25
-
ps
65
-
100
-
ps
180
-
200
-
ps
165
0.4
-
0.38
0.45
0.45
-255
-
-
125
-
0.55
0.55
+255
200
0.49
-
0.38
0.45
0.45
-300
-
-
150
-
0.55
0.55
300
ps
ns
ps
tCK
(AVG)
tCK
tCK
ps
1
10
1
10
ns
0.2
-
0.2
0.2
0.9
0.3
0.9
0.3
- 0.25
-
Note1
Note2
-
-
+ 0.25
0.2
0.9
0.3
0.9
0.3
- 0.25
620
-
780
65
-
125
240
-
300
-
tCK
-
tCK
Note1 tCK
Note2 tCK
-
tCK
-
tCK
+ 0.25 tCK
-
ps
-
ps
-
ps
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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