MMC3316XMT Datasheet, PDF (9/13 Pages) List of Unclassifed Manufacturers – The MMC3316xMT is a complete 3-axis magnetic sensor with on-chip signal processing and integrated I2C bus.

DATA TRANSFER
A data transfer is started with a “START” condition and
ended with a “STOP” condition. A “START” condition
is defined by a HIGH to LOW transition on the SDA
line while SCL line is HIGH. A “STOP” condition is
defined by a LOW to HIGH transition on the SDA line
while the SCL line is held HIGH. All data transfer in I²C
system are 8-bits long. Each byte has to be followed
by an acknowledge bit. Each data transfer involves a
total of 9 clock cycles. Data is transferred starting with
the most significant bit (MSB). After a “START”
condition, the master device calls a specific slave
device, in our case, a MEMSIC device with a 7-bit
device address [0110xxx]. To avoid potential address
conflicts, either by ICs from other manufacturers or by
other MEMSIC devices on the same bus, a total of 8
different addresses can be pre-programmed into
MEMSIC device by the factory. Following the 7-bit
address, the 8^th bit determines the direction of data
transfer: [1] for READ and [0] for WRITE. After being
addressed, the MEMSIC device should respond with
an “Acknowledge” signal, which pulls the SDA line
LOW.
In order to read the sensor signal, a master device
should initiate a WRITE action with a code of
[xxxxxxx1] into the MEMSIC device‟s 8-bit internal
control register 0. Note that this action also serves as
a “wake-up” call.
After writing the code [xxxxxxx1] into Internal Control
0, and the bit0 TM (Status Register, bit 0) is „1‟, also a
“READ” command is received, the MEMSIC device
being called transfers 8-bit data to I²C bus.
POWER STATE
MEMSIC MR Sensor will enter power down mode
automatically after data acquisition is finished.
VDA
OFF(0V)
OFF(0V)
1.62~3.6V
1.62~3.6V
VDD
OFF(0V)
1.62~3.6V
OFF(0V)
1.62~3.6V
Power State
OFF(0V), no power
consumption
OFF(0V),
power
consumption is less than
1uA.
Power consumption is not
predictable,
not
recommended state.
Normal operation mode,
device will enter into
power down mode
automatically after data
acquisition is finished
EXAMPLE MEASUREMENT
First cycle: A START condition is established by the
Master Device followed by a call to the slave address
[0110xxx] with the eighth bit held low to indicate a
WRITE request. Note: [xxx] is determined by factory
programming and a total of 8 different addresses are
available.
Second cycle: After an acknowledge signal is received
by master device (MEMSIC device pulls SDA line low
during 9^th SCL pulse), the master device sends the
address of Control Register 0 or [00000111] as the
target register to be written. The MEMSIC device
should acknowledge at the end (9^th SCL pulse, SCL
pulled low).
Third cycle: The Master device writes to the Internal
Control Register 0 the code [00000001] as a wake-up
call to initiate a data acquisition. The MEMSIC device
should send an Acknowledge.
A STOP condition indicates the end of the write
operation.
Fourth cycle: The Master device sends a START
command followed by the MEMSIC device‟s seven bit
address, and finally the eighth bit set low to indicate a
WRITE. An Acknowledge should be send by the
MEMSIC device in response.
Fifth cycle: The Master device sends the MEMSIC
device‟s Status Register [00000110] as the address to
read.
Sixth cycle: The Master device sends a START
command followed by the MEMSIC device‟s seven bit
address, and finally the eighth bit set high to indicate a
READ. An Acknowledge should be send by the
MEMSIC device in response.
Seventh cycle: The Master device cycles the SCL line.
This causes the Status Register data to appear on
SDA line. Continuously read the Status Register until
the Meas Done bit is set to „1‟.
Eighth cycle: The Master device sends a START
command followed by the MEMSIC device‟s seven bit
address, and finally the eighth bit set low to indicate a
WRITE. An Acknowledge should be send by the
MEMSIC device in response.
Ninth cycle: The Master device sends a [00000000]
(Xout LSB register address) as the register address to
read.
Tenth cycle: The Master device calls the MEMSIC
device‟s address with a READ (8^th SCL cycle SDA line
high). An Acknowledge should be send by the
MEMSIC device in response.
MEMSIC MMC3316xMT Rev.A
Page 9 of 13
8/10/2012