L138-DI-225-RI Datasheet, PDF (9/13 Pages) List of Unclassifed Manufacturers – MityDSP-L138F Processor Card

Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
Signal / Group
I/O
USB0_XXXX,
I/O
USB1_XXXX
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
Description
be tied to the desired voltage used for the FPGA
Bank 0 or 1 interface pins. Please refer to the
VCCO input pin specifications for the Xilinx
Spartan 6 family of devices for further information.
Typical values are 3.3V and 2.5 volts.
The USBN_ prefixed pins are direct connects to the
corresponding pins on the OMAP-L138 processor.
For details please refer to the OMAP-L138 processor
specifications.
DEBUG INTERFACE
Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with
an available adapter board, CL part number 80-000286, to debug the OMAP-L138 and
FPGA.
Debug Interface Connector Description (J2)
Table 3 OMAP-L138 Hirose Connector
Pin I/O
Signal
Pin I/O
Signal
1
- GND
2
O OMAP EMU1
3
- GND
4
O OMAP EMU0
5
- GND
6
I OMAP TCK
7
- GND
8
O OMAP RTCK
9
- GND
10 O OMAP TDO
11
- GND
12 - OMAP VCC / 3.3V
13
- GND
14 I OMAP TDI
15
- GND
16 I OMAP TRST
17
- GND
18 I OMAP TMS
19
- GND
20 - GND
21
- GND
22 O FPGA VREF / VCCAUX
23
- GND
24 I FPGA TMS
25
- GND
26 I FPGA TCK
27
- GND
28 O FPGA TDO
29
- GND
30 I FPGA TDI
31
- GND
9
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Specifications Subject to Change