L138-DI-225-RI Datasheet, PDF (3/13 Pages) List of Unclassifed Manufacturers – MityDSP-L138F Processor Card

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MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
FPGA Bank I/O
The MityDSP-L138F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card
edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA
at the end user’s discretion.
With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled
banks may be configured to operate on a different electrical interface standard based on
input voltage provided at the card edge connector. The banks support 3.3V, 2.5V, and
1.8V standard CMOS switching level technology. In addition, the I/O lines from the
FPGA have been routed as differential pairs and support higher speed LVDS standards as
well as SSTL 2.5 switching standards. Various forms of termination (pull-up/pull-down,
digitally controlled impedance matching) are available within the FPGA switch fabric.
Refer to the Xilinx Spartan 6 user’s guide for more information.
OMAP-L138 mDDR2 Memory Interface
The OMAP-L138 includes a dedicated DDR2 SDRAM memory interface shared between
the onboard ARM and DSP cores. The MityDSP-L138F includes up to 256 MB of
mDDR2 RAM integrated with the OMAP-L138 processor. The bus interface is capable
of burst transfer rates of 600 MB / second. Note that the OSCIN frequency to the OMAP-
L138 processor on the module is 24MHz.
OMAP-L138 SPI NOR FLASH Interface
The MityDSP-L138F includes 8 MB of SPI NOR FLASH. This FLASH memory is
intended to store a factory provided bootloader, and typically a compressed image of a
Linux kernel for the ARM core processor.
EMIFA - FPGA / NAND FLASH Interface
The OMAP-L138 and the Spartan-6 FPGA are connected using the DSP Asynchronous
External Memory Interface (EMIFA). The EMIFA interface includes 3 chip select
spaces. The EMIF interface supports multiple data width transfers and bus wait state
configurations based on chip select space. 8, and 16 bit data word sizes may be used.
Two of the three chip select lines (CE2, CE3) are reserved for the FPGA interface. The
MityDSP-L138F also includes 4 lines between the FPGA and the OMAP for the purposes
of generating interrupt signals.
In addition to the FPGA, up to 512 MB of on-board NAND FLASH memory is
connected to the OMAP-L138 using the EMIFA bus. The FLASH memory is 8 bits wide
and is connected to third chip select line of the EMIFA (CE1). The FLASH memory is
typically used to store the following types of data:
- ARM Linux / Windows Embedded CE / QNX embedded root file-system
- FPGA application images
- runtime DSP or ARM software
- runtime application data (non-volatile storage)
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