L138-DI-225-RI Datasheet, PDF (8/13 Pages) List of Unclassifed Manufacturers – MityDSP-L138F Processor Card

Critical Link, LLC
www.CriticalLink.com
www.MityDSP.com
MityDSP
MityDSP-L138F Processor Card
29-AUG-2013
Signal / Group
3.3 V in
EXT_BOOT#
RESET_IN#
SPI_XXXX
MII_XXXX
MDIO_XX
GP0_X
SATA_TX_P/N
SATA_RX P/N
GND
BX_Y_P.ZZ,
BX_Y_N.ZZ
VCCO_X
Table 2 Signal Group Description
I/O
Description
N/A 3.3 volt input power referenced to GND.
I
Bootstrap configuration pin. Pull low to configure
booting from external UART1.
I
Manual Reset. When pulled to GND for a minimum
of 1 usec, resets the DSP processor.
I/O The pins with an SPI_ prefix are direct connections
to the OMAP-L138 pins supporting the SPI1
interface. The SPI1_CLK, SPI1_ENA, SPI1_MISO,
SPI1_MOSI pins must remain configured for the SPI
function in order to support interfacing to the on-
board SPI boot ROM. For details please refer to the
OMAP-L138 processor specifications.
I/O The pins with an MII_ prefix are direct connections
to the OMAP-L138 pins supporting the media
independent interface (MII) function. The MII pins
provide multiplex capability and may alternately be
used as UART, GPIO, and SPI control pins. For
details please refer to the OMAP-L138 processor
specification.
I/O The MDIO_CLK and MDIO_DAT signals are direct
connects to the corresponding MDIO signals on the
OMAP-L138 processor. These pins may be
configured for GPIO.
IO General Purpose / multiplexed pins. These pins are
direct connects to the corresponding GP0[X] pins on
the OMAP-L138 processor. The include support for
the McASP, general purpose I/O, UART flow
control, and McBSP 1. For details please refer to the
OMAP-L138 processor specifications.
O These pins are direct connects to the OMAP-L138
SATA_TX differential Serial ATA controller pins.
I
These pins are direct connects to the OMAP-L138
SATA_RX differential Serial ATA controller pins.
N/A System Digital Ground.
IO FPGA I/O pins. These pins are routed directly to
FPGA pins ZZ. The “X” indicates which FPGA
bank the pin is allocated. The bank is either 0 or 1.
The FPGA fabric supports routing pins in
differential pairs, the Y_P and Y_N portion of the
name indicates the pair number and polarity. The
pins have been routed in pairs with phase matched
line lengths.
I
FPGA Bank interface power input. These pins must
8
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Specifications Subject to Change