ISP1763AETTM Datasheet, PDF (82/134 Pages) List of Unclassifed Manufacturers – Hi-Speed USB OTG controller Rev. 02 — 24 February 2011

ISP1763A
Hi-Speed USB OTG controller
Table 87.
Bit
7 to 0
DW3
63
62
61
60
59
58
57
56 to 55
54 to 44
43 to 32
DW2
31 to 24
23 to 8
7 to 0
DW1
63 to 57
56 to 50
49 to 48
47
Start and complete split for interrupt: bit description …continued
Symbol
Access
Value Description
SA[7:0]
SW — writes -
(0  1)
HW — writes
(1  0)
SA: Specifies which SOF the start split needs to be placed.
For OUT token: When the frame number of bits DW2[7:3]
matches the frame number of the USB bus, these bits are
checked for one before they are sent for SOF.
After
processing
For IN token: Only SOF0, SOF1, SOF2, or SOF3 can be set
to 1. Nothing can be set for SOF4 and above.
A
H
B
X
SC
reserved
DT
Cerr[1:0]
SW — sets
-
HW — resets
HW — writes -
HW — writes -
HW — writes -
SW — writes 0 -
HW — updates
-
-
HW — writes -
SW — writes
HW — writes -
SW — writes
reserved
-
-
NrBytes
HW — writes -
Transferred[11:0]
Active: Write the same value as that in V.
Halt: The Halt bit is set when any microframe transfer status has a
stalled or halted condition.
Babble: This bit corresponds to bit 1 of Status0 to Status7 for
every microframe transfer status.
Transaction error: This bit corresponds to bit 0 of Status0 to
Status7 for every microframe transfer status.
Start/complete:
0 — Start split
1 — Complete split
-
Data toggle: For an interrupt transfer, set correct bit to start the
PTD.
Error counter: This field corresponds to the Cerr[1:0] field in TD.
00 — The transaction will not retry.
11 — The transaction will retry three times. The hardware will
decrement these values.
-
Number of bytes transferred: This field indicates the number of
bytes sent or received for this transaction.
reserved
DataStart
Address[15:0]
Frame[7:0]
-
-
SW — writes -
SW — writes -
-
Data start address: This is the start address for data that will be
sent on or received from the USB bus. This is the internal memory
address and not the CPU address.
Frame: Bits 7 to 3 is the polling rate in milliseconds. Polling rate
is defined as 2^{(b  1)} SOF; where b = 4 to 16. Executed every
millisecond when b is 4. See Table 88.
HubAddress[6:0] SW — writes -
PortNumber[6:0] SW — writes -
SE[1:0]
SW — writes -
reserved
-
-
Hub address: This indicates the hub address.
Port number: This indicates the port number of the hub or
embedded TT.
This depends on the endpoint type and direction. It is valid only for
split transactions. Table 89 applies to start split and complete split
only.
-
CD00264885
Product data sheet
Rev. 02 — 24 February 2011
© ST-ERICSSON 2011. All rights reserved.
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