ISP1763AETTM Datasheet, PDF (56/134 Pages) List of Unclassifed Manufacturers – Hi-Speed USB OTG controller Rev. 02 — 24 February 2011

ISP1763A
Hi-Speed USB OTG controller
Table 67.
Bit
15 to 11
10
9
8
7
6
5
4
3
2
1
0
HcInterruptEnable - Host Controller Interrupt Enable register (address D6h) bit description
Symbol
Description
-
reserved
OTG_IRQ_E
OTG IRQ enable: Controls the INT assertion because of events present in the OTG Interrupt
Latch register.
0 — No INT will be asserted.
1 — INT will be asserted.
For details, see Section 8.9.3.
ISO_IRQ_E
ISO IRQ enable: Controls the INT assertion when one or more ISO PTDs matching the ISO
IRQ Mask AND or ISO IRQ Mask OR register bits combination are completed.
0 — No INT will be asserted when ISO PTDs are completed.
1 — INT will be asserted.
For details, see Section 8.9.3.
ATL_IRQ_E
ATL IRQ enable: Controls the INT assertion when one or more ATL PTDs matching the ATL
IRQ Mask AND or ATL IRQ Mask OR register bits combination are completed.
0 — No INT will be asserted when ATL PTDs are completed.
1 — INT will be asserted.
For details, see Section 8.9.3.
INT_IRQ_E
INT IRQ enable: Controls the INT assertion when one or more INT PTDs matching the INT
IRQ Mask AND or INT IRQ Mask OR register bits combination are completed.
0 — No INT will be asserted when INT PTDs are completed.
1 — INT will be asserted.
For details, see Section 8.9.3.
CLKREADY_E Clock ready enable: Enables the INT assertion when internal clock signals are running
stable. Useful after wake-up.
0 — No INT will be generated after CLKREADY_E event.
1 — INT will be generated after a CLKREADY_E event.
HCSUSP_E
Host controller suspend enable: Enables the INT generation when the host controller
enters suspend mode.
0 — No INT will be generated when the host controller enters suspend mode.
1 — INT will be generated when the host controller enters suspend mode.
OPR_REG_E Operational registers enable: Controls the INT generation because of at least one change
in operational registers.
0 — No INT will be generated on any change in operational registers.
1 — INT will be generated after a bit change, set by the software or hardware internally
modified by the host controller, in the operational registers.
DMAEOT
INT_E
DMA EOT interrupt enable: Controls assertion of INT on the DMA transfer completion.
0 — No INT will be generated when a DMA transfer is completed.
1 — INT will be asserted when a DMA transfer is completed.
-
reserved
SOFINT_E
SOF interrupt enable: Controls the INT generation at every SOF occurrence.
0 — No INT will be generated on SOF occurrence.
1 — INT will be asserted at every SOF.
MSOFINT_E SOF interrupt enable: Controls the INT generation at every SOF occurrence.
0 — No INT will be generated on SOF occurrence.
1 — INT will be asserted at every SOF.
CD00264885
Product data sheet
Rev. 02 — 24 February 2011
© ST-ERICSSON 2011. All rights reserved.
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