ISP1763AETTM Datasheet, PDF (130/134 Pages) List of Unclassifed Manufacturers – Hi-Speed USB OTG controller Rev. 02 — 24 February 2011

ISP1763A
Hi-Speed USB OTG controller
register (address 1Eh) bit allocation . . . . . . . .93
Table 108.DcBufferStatus - Device Controller Buffer Status
register (address 1Eh) bit description . . . . . . .93
Table 109.ENDP_MAXPKTSIZE - Endpoint MaxPacketSize
register (address 04h) bit allocation . . . . . . . . .93
Table 110. ENDP_MAXPKTSIZE - Endpoint MaxPacketSize
register (address 04h) bit description . . . . . . .94
Table 111. ENDP_TYPE - Endpoint Type register (address
08h) bit allocation . . . . . . . . . . . . . . . . . . . . . .94
Table 112. ENDP_TYPE - Endpoint Type register (address
08h) bit description . . . . . . . . . . . . . . . . . . . . .95
Table 113. Control bits for GDMA read/write
(opcode = 00h/01h) . . . . . . . . . . . . . . . . . . . . .96
Table 114. DMA_CMD - DMA Command register (address
30h) bit allocation . . . . . . . . . . . . . . . . . . . . . .96
Table 115. DMA_CMD - DMA Command register (address
30h) bit description . . . . . . . . . . . . . . . . . . . . .96
Table 116. DMA commands . . . . . . . . . . . . . . . . . . . . . . .96
Table 117. DMA_XFR_CTR - DMA Transfer Counter register
(address 34h) bit allocation . . . . . . . . . . . . . . .97
Table 118. DMA_XFR_CTR - DMA Transfer Counter register
(address 34h) bit description . . . . . . . . . . . . . .98
Table 119. DcDMAConfiguration - Device Controller Direct
Memory Access Configuration register (address
38h) bit allocation . . . . . . . . . . . . . . . . . . . . . .98
Table 120.DcDMAConfiguration - Device Controller Direct
Memory Access Configuration register (address
38h) bit description . . . . . . . . . . . . . . . . . . . . .98
Table 121.DMA_HW - DMA Hardware register (address
3Ch) bit allocation . . . . . . . . . . . . . . . . . . . . . .99
Table 122.DMA_HW - DMA Hardware register (address
3Ch) bit description . . . . . . . . . . . . . . . . . . . . .99
Table 123.DMA_INTR_REASON - DMA Interrupt Reason
register (address 50h) bit allocation . . . . . . . . .99
Table 124.DMA_INTR_REASON - DMA Interrupt Reason
register (address 50h) bit description . . . . . .100
Table 125.Internal EOT-functional relation with bit
DMA_XFER_OK . . . . . . . . . . . . . . . . . . . . . .100
Table 126. Status of the bits in the DMA Interrupt Reason
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 127.DMA_INTR_EN - DMA Interrupt Enable register
(address 54h) bit allocation . . . . . . . . . . . . . .101
Table 128.DMA_INTR_EN - DMA Interrupt Enable register
(address 54h) bit description . . . . . . . . . . . . .101
Table 129.DMA_ENDP - DMA Endpoint register (address
58h) bit allocation . . . . . . . . . . . . . . . . . . . . .101
Table 130.DMA_ENDP - DMA Endpoint register (address
58h) bit description . . . . . . . . . . . . . . . . . . . .102
Table 131.DMA_BRST_CTR - DMA Burst Counter register
(address 64h) bit allocation . . . . . . . . . . . . . .102
Table 132.DMA_BRST_CTR - DMA Burst Counter register
(address 64h) bit description . . . . . . . . . . . . .102
Table 133.DcInterrupt - Device Controller Interrupt register
(address 18h) bit allocation . . . . . . . . . . . . . .103
Table 134.DcInterrupt - Device Controller Interrupt register
(address 18h) bit description . . . . . . . . . . . . .103
Table 135.DcChipID - Device Controller Chip Identifier
register (address 70h) bit description . . . . . .104
Table 136.FRAME_NO - Frame Number register (address
74h) bit allocation . . . . . . . . . . . . . . . . . . . . . 105
Table 137. FRAME_NO - Frame Number register (address
74h) bit description . . . . . . . . . . . . . . . . . . . . 105
Table 138.SCRATCH - Scratch register (address 78h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 139.SCRATCH - Scratch register (address 78h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 140.UNLOCK_DEV - Unlock Device register (address
7Ch) bit allocation . . . . . . . . . . . . . . . . . . . . . 106
Table 141.UNLOCK_DEV - Unlock Device register (address
7Ch) bit description . . . . . . . . . . . . . . . . . . . . 106
Table 142.INTR_PULSE_WIDTH - Interrupt Pulse Width
register (address 80h) bit description . . . . . . 106
Table 143.TEST_MODE - Test Mode register (address 84h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 144.TEST_MODE - Test Mode register (address 84h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 145.Limiting values . . . . . . . . . . . . . . . . . . . . . . . 108
Table 146.Recommended operating conditions . . . . . . 108
Table 147.Static characteristics: supply pins . . . . . . . . . 109
Table 148.Static characteristics: digital pins . . . . . . . . . 109
Table 149.Static characteristics: USB interface block (pins
DM1, DM2, DP1, DP2) . . . . . . . . . . . . . . . . . 109
Table 150.Static characteristics: V_BUS comparators . . . 110
Table 151.Static characteristics: V_BUS resistors . . . . . . . 111
Table 152.Static characteristics: ID detection circuit . . . 111
Table 153.Dynamic characteristics: system clock . . . . . 112
Table 154.Dynamic characteristics: power-up and reset 112
Table 155.Dynamic characteristics: digital pins . . . . . . . 112
Table 156.Dynamic characteristics: high-speed source
electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 157.Dynamic characteristics: full-speed source
electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 158.Dynamic characteristics: low-speed source
electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 159.DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 160.PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 161.PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 162.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 163.Revision history . . . . . . . . . . . . . . . . . . . . . . . 127
CD00264885
Product data sheet
Rev. 02 — 24 February 2011
© ST-ERICSSON 2011. All rights reserved.
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