ISP1763AETTM Datasheet, PDF (21/134 Pages) List of Unclassifed Manufacturers – Hi-Speed USB OTG controller Rev. 02 — 24 February 2011

ISP1763A
Hi-Speed USB OTG controller
Both the PTD and payload memory zones are divided into three dedicated areas for each
main type of USB transfer: Isochronous (ISO), Interrupt (INT), and Asynchronous Transfer
List (ATL). As shown in Table 7, the PTD areas for ISO, INT, and ATL are grouped at the
beginning of the memory, occupying address range 0400h to 0FFFh, following the
registers address space. The payload or data area occupies the next memory address
range 1000h to 5FFFh, meaning that 20 kB of memory is allocated for the payload data.
A maximum of 16 PTD areas and their allocated payload areas can be defined for each
type of transfer. The structure of a PTD is similar for every transfer type and consists of
eight Double Words (DWs) that must be correctly programmed for correct USB data
transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the
PTD structure can be found in Section 10.4.
The transfer size specified by the PTD determines the contiguous USB data transfer that
can be performed without any CPU intervention. The respective payload memory area
must be equal to the transfer size defined. The maximum transfer size is flexible and can
be optimized, depending on the number and nature of USB devices or PTDs defined and
their respective MaxPacketSize.
The RAM is structured in blocks of PTDs and payloads so that while the USB is executing
on an active transfer-based PTD, the processor can simultaneously fill up another block
area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping
or delaying any other USB transaction or corrupting the RAM data.
Some of the design features are:
• The internal memory contains isochronous, interrupt, and asynchronous PTDs, and
defined payloads.
• Internal memory address range calculation:
Memory address = (CPU address  0400h) (shift right >> 3). The base address is
0400h.
Table 7. Memory address
Memory map CPU address Memory address
ISO PTD
0400h to 05FFh 0000h to 007Fh
INT PTD
0800h to 09FFh 0080h to 00FFh
ATL PTD
0C00h to 0DFFh 0100h to 017Fh
Payload
1000h to 5FFFh 0180h to 0B7Fh
Memory accessing
• Configure the Memory register
– Bits 14 to 0: start address 1000h to 5FFFh
– Bit 15: reserved
• Read/write data from or to the Data register (address C6h of
the ISP1763A).
• The memory burst read and write is ended by any register
access (other than C6h).
Both the CPU interface logic and the USB host controller require access to the internal
ISP1763A RAM at the same time. The internal arbiter controls these accesses to the
internal memory, organized internally on a 64-bit data bus width, allowing a maximum
bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the
CPU interface and the internal USB host controller.
CD00264885
Product data sheet
Rev. 02 — 24 February 2011
© ST-ERICSSON 2011. All rights reserved.
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