24A01 Datasheet, PDF (8/24 Pages) List of Unclassifed Manufacturers – 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power

BYTE WRITE OPERATION
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the TMC 24A01/24A02/24A04/24A08/24A16 slave device (see Figure 3-9).
Start Slave Address
Word Address
Data
Stop
A
A
A
C
C
C
K
K
K
Figure 3-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed TMC 24A01/24A02/24A04/24A08/24A16 generates an ACK
and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address
is written into the word address pointer of the TMC 24A01/24A02/24A04/24A08/24A16.
When the TMC 24A01/24A02/24A04/24A08/24A16 receives the word address, it responds by issuing an ACK
and then waits for the next 8-bit data. When it receives the data byte, the
TMC 24A01/24A02/24A04/24A08/24A16 again responds with an ACK. The master terminates the transfer by
generating a Stop condition, at which time the TMC 24A01/24A02/24A04/24A08/24A16 begins the internal write
cycle.
While the internal write cycle is in progress, all TMC 24A01/24A02/24A04/24A08/24A16 inputs are disabled and
the TMC 24A01/24A02/24A04/24A08/24A16 does not respond to additional requests from the master.
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