24A01 Datasheet, PDF (7/24 Pages) List of Unclassifed Manufacturers – 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power

Master
SCL Line
Data from
Transmitter
ACK from
Receiver
Bit 1
Bit 9
ACK
Figure 3-8. Acknowledge Response From Receiver
• Slave Address: After the master initiates a Start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier
for the TMC 24A01/24A02/24A04/24A08/24A16 is “1010B”. The next three bits comprise the address of a
specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing
scheme, you can cascade up to eight TMC 24A01/24A02 or four TMC 24A04 or two TMC 24A08 or one
TMC 24A16 on the bus (see Table 3-2 below). The b1 for TMC 24A04 or the b1, b2 for TMC 24A08 or the
b1, b2, b3 for TMC24A16 are used by the master to select which of the blocks of internal memory (1 block
= 256 words) are to be accessed. The bits are in effect the most significant bits of the word address.
• Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Table 3-2. Slave Device Addressing
Device
TMC24A01/24A02
TMC24A04
TMC24A08
TMC24A16
Device Identifier
b7 b6 b5 b4
1010
1010
1010
1010
Device Address
b3
b2
b1
A2
A1
A0
A2
A1
B0
A2
B1
B0
B2
B1
B0
NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word.
R/W Bit
b0
R/W
R/W
R/W
R/W
7