24A01 Datasheet, PDF (11/24 Pages) List of Unclassifed Manufacturers – 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power

HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the TMC 24A01/24A02/24A04/24A08/24A16. This method
of write protection is controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to V_CC, any attempt to write a value to the memory is ignored.
The TMC 24A01/24A02/24A04/24A08/24A16 will acknowledge slave and word address, but it will not generate
an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop
condition is generated. By connecting the WP pin to V_SS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the TMC 24A01/24A02/24A04/24A08/24A16receives a slave address with the R/W bit set to “1”, it issues
an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a
Stop condition. In this way, the TMC 24A01/24A02/24A04/24A08/24A16 effectively stops the transmission (see
Figure 3-12).
Start Slave Address
Data
Stop
A
N
C
O
K
A
C
K
Figure 3-12. Current Address Byte Read Operation
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