24A01 Datasheet, PDF (12/24 Pages) List of Unclassifed Manufacturers – 1K/2K/4K/8K/16K-bit Serial EEPROM for Low Power

RANDOM ADDRESS BYTE READ OPERATION
Using random read operations, the master can access any memory location at any time. Before it issues the
slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This operation
is performed in the following steps:
1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets
the internal word address pointer of the TMC 24A01/24A02/24A04/24A08/24A16 to the desired address.)
2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed
by another slave address, with the R/W bit set to “1”.
3. The TMC 24A01/24A02/24A04/24A08/24A16 then sends an ACK and the 8-bit data stored at the desired
address.
4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead.
5. In response, the TMC 24A01/24A02/24A04/24A08/24A16 stops transmitting data and reverts to its stand-by
mode (see Figure 3-13).
Start Slave Address
Word Address
Start Slave Address
Data (n)
Stop
A
A
C
C
K
K
A
N
C
O
K
A
C
K
Figure 3-13. Random Address Byte Read Operation
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