EP1S20F672C7N Datasheet, PDF (747/864 Pages) List of Unclassifed Manufacturers – Stratix Device Handbook, Volume 1

Configuring Stratix & Stratix GX Devices
FPP Configuration Timing
Figure 11–15 shows FPP timing waveforms for configuring a Stratix or
Stratix GX device in FPP mode. Table 11–9 shows the FPP timing
parameters for Stratix or Stratix GX devices.
Figure 11–15. Timing Waveform for Configuring Devices in FPP Mode Note (1)
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA[7..0}
User I/O
INIT_DONE
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Byte 0 Byte 1 Byte 2 Byte 3
t_DSU
High-Z
Byte n
(4)
(4)
User Mode
User Mode
t_CD2UM
Notes to Figure 11–15:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)
Symbol
Parameter
t_CF2CK
t_DSU
t_DH
t_CFG
t_CH
t_CL
t_CLK
nCONFIG high to first rising edge on DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
nCONFIG low pulse width
DCLK high time
DCLK low time
DCLK period
Min
Max
40
7
0
40
4
4
10
Units
µs
ns
ns
µs
ns
ns
ns
Altera Corporation
July 2005
11–29
Stratix Device Handbook, Volume 2