EP1S20F672C7N Datasheet, PDF (547/864 Pages) List of Unclassifed Manufacturers – Stratix Device Handbook, Volume 1

High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer
Counter
Data[7..0]
Clock
×4 clock
PLL
×1 clock
Shift
Register
clock
load
data
data_l
Shift
Register
data
data_h
load
clock
DDR
Output
Serial
data out
tx_clk
Summary
The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOPC) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stratix devices can easily implement processing-intensive data-
path functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
Altera Corporation
July 2005
5–75
Stratix Device Handbook, Volume 2