EP1S20F672C7N Datasheet, PDF (502/864 Pages) List of Unclassifed Manufacturers – Stratix Device Handbook, Volume 1

Source-Synchronous Timing Budget
Source-
Synchronous
Timing Budget
■ After the pattern detection state machine, use another synchronizing
register to capture the generated SYNC signal and synchronize it to
the ×1 clock.
■ Since the skew in the path from the output of this synchronizing
register to the PLL is undefined, the state machine must generate a
pulse that is high for two ×1 clock periods.
■ Since the SYNC generator circuitry only generates a single fast clock
period pulse for each SYNC pulse, you cannot generate additional
SYNC pulses until the comparator signal is reset low.
■ To guarantee the pattern detection state machine does not incorrectly
generate multiple SYNC pulses to shift a single bit, the state machine
must hold the SYNC signal low for at least three ×1 clock periods
between pulses.
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix devices. LVDS, LVPECL,
PCML, and HyperTransport I/O standards enable high-speed data
transmission. This high data-transmission rate results in better overall
system performance. To take advantage of fast system performance, you
must understand how to analyze timing for these high-speed signals.
Timing analysis for the differential block is different from traditional
synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times, source-
synchronous timing analysis is based on the skew between the data and
the clock signals. High-speed differential data transmission requires you
to use timing parameters provided by IC vendors and to consider board
skew, cable skew, and clock jitter. This section defines the source-
synchronous differential data orientation timing parameters, and timing
budget definitions for Stratix devices, and explains how to use these
timing parameters to determine a design's maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 840 Mbps and W = 10, the external clock is
multiplied by 10 and phase-aligned by the PLL to coincide with the
sampling window of each data bit. The third falling edge of high-
frequency clock is used to strobe the incoming high-speed data.
Therefore, the first two bits belong to the previous cycle. Figure 5–23
shows the data bit orientation of the ×10 mode as defined in the
Quartus II software.
5–30
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005