EP1S20F672C7N Datasheet, PDF (234/864 Pages) List of Unclassifed Manufacturers – Stratix Device Handbook, Volume 1

Timing Model
Tables 4–91 through 4–96 show the external timing parameters on column
and row pins for EP1S80 devices.
Table 4–91. EP1S80 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
Parameter
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Min
Max
-8 Speed Grade
Unit
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
2.328
2.528
2.900
NA
ns
0.000
0.000
0.000
NA
ns
2.422 4.830 2.422 5.169 2.422 5.633
NA
NA
ns
2.362 4.704 2.362 5.037 2.362 5.509
NA
NA
ns
2.362 4.704 2.362 5.037 2.362 5.509
NA
NA
ns
Table 4–92. EP1S80 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
Parameter
-5 Speed Grade
Min
Max
-6 Speed Grade
Min
Max
-7 Speed Grade
Min
Max
-8 Speed Grade
Unit
Min
Max
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
1.760
1.912
2.194
NA
0.000
0.000
0.000
NA
2.761 5.398 2.761 5.785 2.761 6.339
NA
2.701 5.272 2.701 5.653 2.701 6.215
NA
2.701 5.272 2.701 5.653 2.701 6.215
NA
0.462
0.606
0.785
NA
0.000
0.000
0.000
NA
1.661 2.849 1.661 2.859 1.661 2.881
NA
1.601 2.723 1.601 2.727 1.601 2.757
NA
1.601 2.723 1.601 2.727 1.601 2.757
NA
ns
ns
NA
ns
NA
ns
NA
ns
ns
ns
NA
ns
NA
ns
NA
ns
4–54
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006