RF63 Datasheet, PDF (72/91 Pages) List of Unclassifed Manufacturers – Ultra-Low Power Integrated UHF Transceiver

ADVANCED COMMUNICATIONS & SENSING
RF63
7.4. Reset of the Chip
A power-on reset of the RF63 is triggered at power up. Additionally, a manual reset can be issued by controlling
pin 13.
7.4.1. POR
If the application requires the disconnection of VDD from the RF63, despite of the extremely low Sleep Mode
current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over
the SPI bus. Pin 13 (TEST8) should be left floating during the POR sequence.
VDD
Pin 13
(output)
Undefined
Wait for Chip is ready from
10 ms this point on
Figure 54: POR Timing Diagram
Please note that any CLKOUT activity can also be used to detect that the chip is ready.
7.4.2. Manual Reset
A manual reset of the RF63 is possible even for applications in which VDD cannot be physically disconnected.
Pin 13 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms
before using the chip.
VDD
Pin 13
(input)
> 100 us
High-Z ‟‟1‟‟
Wait for
5 ms
High-Z
Chip is ready from
this point on
Figure 55: Manual Reset Timing Diagram
Please note that while pin 13 is driven high, an over current consumption of up to ten milliamps can be seen on
VDD.
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