W55P241 Datasheet, PDF (7/32 Pages) List of Unclassifed Manufacturers – I/O device usable with many different microprocessors through SPI interface

W55P241
Chip
Select
Clock
Idle “0”
Changing data
..…
Latching data
Idle “0”
Data
Output
(MSB first)
Sample
Data
MSB Bit N ^..… Bit M LSB
..…
Figure 3 SPI mode 0 (MSB first)
5.1.3 Command Protocol
One SPI transfer consists of one command byte and one data byte. Because the 1^st 8 bits of
“transmit data” are regarded as command byte after the falling edge of /CS, it is not possible that /CS
remains “0’ during two successive SPI transfers. The last 8 bits of “transmit data” in one SPI transfer
are regarded as data bytes. For both command byte and data byte to be identified by the W55P241,
MSB (Most Significant Bit) is transferred first. When the microcontroller writes data to W55P241, DO
remains in high impedance state during the whole SPI transfer. When the microcontroller reads data
from the W55P241, DO remains in high impedance state until the data byte is generated.
-7-