SEP01G72J2BF1SA-37R Datasheet, PDF (6/14 Pages) List of Unclassifed Manufacturers – 1GB DDR2 . SDRAM registered DIMM

Data Sheet
Rev.1.0 20.11.2010
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
V_DDL Supply Voltage
Voltage on any pin relative to V_SS
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
SYMBOL
V_DD
V_DDQ
V_DDL
V_in, V_out
I_I
Command/Address
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
I_OZ
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
V_REF LEAKAGE CURRENT ; V_REF is on a valid level
I_VREF
MIN
-1.0
-0.5
-0.5
-0.5
-40
-20
-5
-5
-16
MAX
2.3
2.3
2.3
2.3
40
20
5
5
UNITS
V
V
V
V
µA
µA
16
µA
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
V_DDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V_DD
V_DDQ
V_DDL
V_REF
V_TT
V_{IH (DC)}
V_{IL (DC)}
MIN
1.7
1.7
1.7
0.49 x V_DDQ
V_REF – 0.04
V_REF + 0.125
-0.3
NOM
1.8
1.8
1.8
0.50 x V_DDQ
V_REF
MAX
1.9
1.9
1.9
0.51x V_DDQ
V_REF + 0.04
V_DDQ + 0.3
V_REF – 0.125
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V_{IH (AC)}
V_{IL (AC)}
MIN
V_REF + 0.25
-
MAX
-
V_REF - 0.25
UNITS
V
V
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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