SEP01G72J2BF1SA-37R Datasheet, PDF (11/14 Pages) List of Unclassifed Manufacturers – 1GB DDR2 . SDRAM registered DIMM

Data Sheet
Rev.1.0 20.11.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
ODT power-down exit
latency
t_AXPD
ODT enable from MRS
command
t_MOD
Exit active power-down to t_XARD
READ command, MR [bit 12
= 0]
Exit active power-down to t_XARDS
READ command, MR [bit 12
= 1]
Exit precharge power-down t_XP
to any non-READ command
CKE minimum high/low time t_CKE
MIN
8
0
2
7 – AL
2
3
MAX
12
4200-444
MIN MAX
8
0
12
2
6 – AL
2
3
Unit
tCK
ns
tCK
tCK
tCK
tCK
Register Specifications
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Symbol
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
VOH
VOL
II
IDD
Pins
Address,
control,
command
Address,
control,
command
Address,
control,
command
Address,
control,
command
Parity
output
Parity
output
All pins
All pins
IDD
All pins
IDDD
n/a
IDDD
n/a
CI
Data
CI
RESET#
Conditions
SSTL_18
SSTL_18
SSTL_18
SSTL_18
LVCMOS
LVCMOS
VI = VDDQ or VSSQ
RESET# = VSSQ (IO = 0)
RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle
RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle;
One data input switching at
tCK/2, 50% duty cycle
VI = VREF ±250mV;
VDDQ = 1.8V
VI = VDDQ or VSSQ
Min
Max
Units
VREF(DC) + 125 VDDQ + 250 mV
0
VREF(DC) - 125 mV
VREF(DC) + 250
VDD
mV
0
VREF(DC) - 250 mV
1.2
-
V
-
0.5
V
-5
+5
µA
-
100
µA
-
40
mA
-
Varies by
manufacturer
µA
-
Varies by
manufacturer
µA
2.5
3.5
pF
-
Varies by
manufacturer
pF
Notes: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2
SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the
module. Detailed information for this register is available in JEDEC standard JESD82.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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