SEP01G72J2BF1SA-37R Datasheet, PDF (2/14 Pages) List of Unclassifed Manufacturers – 1GB DDR2 . SDRAM registered DIMM

Data Sheet
Rev.1.0 20.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR2 registered SDRAM Dual-In-line Memory
Module (RDIMM) which is organized as x72 high speed CMOS memory arrays. All control and address signals
are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM timing. De-coupling capacitors, stub resistors,
calibration resistors and termination resistors are mounted on the PCB board. The module uses double data rate
architecture to achieve high-speed operation. DDR2 SDRAM modules operate from a differential clock (CK and
CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. The burst length is
either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge
that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which
allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a
power-saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
128M x 72bit
DDR2 SDRAMs used
9 x 128M x 8bit (1Gbit)
Row
Addr.
14
Device Bank
Select
Column
Addr.
Refresh
Module
Bank Select
BA0, BA1, BA2 10
8k
S0#
Timing Parameters
Part Number
SEP01G72J2BF1SA-37R
SEP01G72J2BF1SA-30R
Module Dimensions
in mm
133.33 (long) x 30(high) x 2.7 [max] (thickness)
Module Density
1024 MB
1024 MB
Transfer Rate
4.2 GB/s
5.3 GB/s
Clock Cycle/Data bit rate
3.7ns/533MT/s
3.0ns/667MT/s
Latency
4-4-4
5-5-5
Pin Name
A0 - A13
BA0, BA1, BA2
DQ0 – DQ63
CB0 – CB7
DM0-DM8
RAS#
CAS#
WE#
CKE0
CK0
CK0#
DQS0 – DQS8
DQS0# - DQS8#
S0#
Reset#
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Address Inputs
Bank Address Inputs
Data Input / Output
Check Bits
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Input, positive line
Clock Input, negative line
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Chip Select
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQs are High-Z.
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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