SEP01G72J2BF1SA-37R Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – 1GB DDR2 . SDRAM registered DIMM

Data Sheet
Rev.1.0 20.11.2010
1GB DDR2 – SDRAM registered DIMM
240 Pin RDIMM
SEP01G72J2BF1SA-30R
1GB PC2-5300 in FBGA Technology
RoHS compliant
Options:

Data Rate / Latency
DDR2 533MT/s CL4

DDR2 667MT/s CL5
Marking
-37
-30
 Module Density
1024MB with 9 dies and 1 rank
 Standard Grade (T_A)
(T_C)
0°C to 70°C
0°C to 85°C
Environmental Requirements:
 Operating temperature (TAMBIENT)
Standard Grade
0°C to 70°C
 Operating Humidity
10% to 90% relative humidity, noncondensing
 Operating Pressure
105 to 69 kPa (up to 10000 ft.)
 Storage Temperature
-55°C to 100°C
 Storage Humidity
5% to 95% relative humidity, noncondensing
 Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Features:
 240-pin 72-bit DDR2 registered Dual-In-Line Double Data
Rate Synchronous DRAM Module for server applications
 Module organization: single rank 128M x 72
 VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
 1.8V I/O ( SSTL_18 compatible)
 Serial Presence Detect with EEPROM
 Supports ECC error detection and correction
 JEDEC compatible DDR2 PLL/Register component with
parity bit support for address and control bus
 Gold-contact pad
 This module family is fully pin and functional compatible
to JEDEC. (see www.jedec.org)
 The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
 DDR2 SDRAM component Samsung K4T1G084QF
 128Mx8 DDR2 SDRAM in FBGA-60 package
 Four bit prefetch architecture
 Programmable CAS latency (CL)
 Posted CAS additive latency (AL)
 WRITE latency = READ latency – 1 tCK
 Programmable burst length: 4 or 8
 Adjustable data-output drive strength
 On-die termination (ODT)
 DLL to align DQ and DQS transitions with CK
mechanical dimensions¹
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: [phone]
Fax: [phone]
1 _{if no tolerances specified ± 0.15mm}
www.swissbit.com
eMail: [e-mail]
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