EAEDIP320B-8LW Datasheet, PDF (6/25 Pages) List of Unclassifed Manufacturers – CONTROL UNIT 320x240 WITH INTELLIGENCE

EA eDIP320-8
Page 6
Specifications may be changed without
prior notice. Printing error reserved
SPI INTERFACE
If the display is wired as shown below, SP
mode is activated. The data is then transferred
via the serial, synchronous SPI interface.
Data transfer is possible at up to 100 kHz.
However, if pauses of at least 100 µs are
maintained between the individual bytes
during transfer, a byte can be transferred at
up to 3 MHz.
Note:
The pins DORD, CPOL, CPHA, WUP, DPROT and TEST/SBUF
have an internal pullup, which is why only the LO level
(0=GND) is to be actively applied. These pins must be left open
for a Hi level.
On pin 20 (SBUF) the display indicates with a low level that
data is ready to be retrieved from the internal send buffer. The
line can be connected to an interrupt input of the host system,
for example.
Pinout eDIP320-8: SPI mode
Pin Symbol In/Out Function
Pin Symbol Function
1 GND
- Ground Potential for logic (0V)
25 N.C. not connected
2 VDD
- Power supply for logic (+5V)
26 N.C. not connected
3 VADJ
In Operating voltage for LC driving (input)
27 N.C. not connected
4 VOUT Out Output voltage for LC driving
28 N.C. not connected
5 RESET
- L: Reset
29 N.C. not connected
6
SS
In Slave Select
30 N.C. not connected
7 MOSI
In Serial In
31 N.C. not connected
8 MISO Out Serial Out
32 N.C. not connected
9 CLK
In Shift Clock
33 N.C. not connected
10 DORD In Data Order (0=MSB first; 1=LSB first)
34 N.C. not connected
11 SPIMODE In connect to GND for SPI interface
35 N.C. not connected
12 OUT2 Out open-drain with internal pullup 20..50k
36 N.C. not connected
13 WUP
In
L: (Power-On) disable Power-On-Macro
L: Wakeup from Powerdownmode
37 N.C. not connected
14 CPOL
In Clock Polarity (0=LO 1=HI when idle)
38 N.C. not connected
15 CPHA
In
Clock Phase
(sampled on 0=1st 1=2nd edge)
39 N.C. not connected
16 BUZZ Out Buzzer output
40 N.C. not connected
17 DPROT
In
L: Disable Smallprotokoll
do not connect for normal operation
41 N.C. not connected
18 DPWR
Out
L: Normal Operation
H: Powerdownmode
42 N.C. not connected
19 WP
In L: Writeprotect for DataFlash
43 N.C. not connected
20
TEST
SBUF
IN
Out
open-drain with internal pullup 20..50k
IN (Power-On) L: Testmode
OUT L: data in sendbuffer
44 N.C. not connected
21 PDI
internal use, do not connect
45 N.C. not connected
22 PDO
internal use, do not connect
46 N.C. not connected
23 N.C.
do not connect, reserved
47 N.C. not connected
24 N.C.
do not connect, reserved
48 N.C. not connected
DATA TRANSFER SPI
Via the pins DORD, CPOL and CPHA transfer
parameter will be set.
Write operation: a clock rate up to 100 kHz is allowed
without any stop. Together with a pause of 100 µs
between every data byte a clock rate up to 3 MHz an
be reached.
Read operation: to read data (e.g. the "ACK" byte) a
dummy byte (e.g . 0xFF) need to be sent. Note that the
EA eDIP320-8 for internal operation does need a short
time before providing the data; therefore a short pau-
se of min. 6µs (no activity of CLK line) is needed for
each byte. Same is with 100kHz operation.
application example