AT45DB642D_14 Datasheet, PDF (55/57 Pages) List of Unclassifed Manufacturers – 64-megabit 2.7V Dual-interface DataFlash

AT45DB642D
29. Revision History
Revision Level – Release Date
A – September 2005
B – November 2005
C – March 2006
D – July 2006
E – August 2006
F – August 2006
G – August 2007
H – April 2008
I – February 2009
History
Initial release
Changed t_VCSL from 30µs to 50µs min.
Changed t_PUW from 10ms to 20ms max.
Changed t_DIS from 8ns to 6ns max.
Changed t_V from 8ns to 6ns max.
Added text, in “Programming the Configuration Register”, to indicate
that power cycling is required to switch to “power of 2” page size
after the opcode has been executed.
Corrected typographical errors.
Added errata regarding Chip Erase.
Added t_SCKR and t_SCKF parameters to Table 18-4.
Added additional text for “power of 2” binary page size option.
Changed t_RDPD from 30µs to 35µs.
Added t_CLKR and t_CLKF parameters to Table 18-5.
Added part number ordering code details for suffixes SL954/955.
Added ordering code details.
Changed t_DIS (Typ and Max) to 27ns and 35ns, respectively, for
RapidS interface.
J – March 2009
Changed Deep Power-Down Current values
- Increased typical value from 9µA to 15µA.
- Increased maximum value from 18µA to 25µA.
K – April 2009
Updated Absolute Maximum Ratings
Added 24C1 24 Ball BGA package Option
Deleted DataFlash Card Package Option
L – May 2010
Changed t_SE (Typ) 1.6 to 0.7 and (Max) 5 to 1.3
Changed from 10,000 to 20,000 cumulative page erase/program
operations and added the please contact Adesto statement in
section 11.3.
M-November 2012
N- February 2014
Update all Adesto Logos.
Not Recommended for New Designs.
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3542N–DFLASH–2/2014