AT45DB642D_14 Datasheet, PDF (23/57 Pages) List of Unclassifed Manufacturers – 64-megabit 2.7V Dual-interface DataFlash

AT45DB642D
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit six is a zero, then the data in the main memory page matches
the data in the buffer. If bit six is a one, then at least one bit of the data in the main memory page
does not match the data in the buffer.
Bit one in the Status Register is used to provide information to the user whether or not the sector
protection has been enabled or disabled, either by software-controlled method or hardware-con-
trolled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates
that sector protection has been disabled.
Bit zero in the Status Register indicates whether the page size of the main memory array is con-
figured for “power of 2” binary page size (1024-bytes) or standard DataFlash page size (1056-
bytes). If bit zero is a one, then the page size is set to 1024-bytes. If bit zero is a zero, then the
page size is set to 1056-bytes.
The device density is indicated using bits five, four, three, and two of the status register. For the
AT45DB642D, the four bits are 1111 The decimal value of these four binary bits does not equate
to the device density; the four bits represent a combinational code relating to differing densities
of DataFlash devices. The device density is not the same as the density code indicated in the
JEDEC device ID information. The device density is provided only for backward compatibility.
Table 11-1. Status Register Format
Bit 7
RDY/BUSY
Bit 6
COMP
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
PROTECT
Bit 0
PAGE SIZE
12. Deep Power-down
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pins (SI or IO₇-IO₀). After the last bit of the com-
mand has been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down
operation. After the CS pin is de-asserted, the will device enter the Deep Power-down mode
within the maximum t_EDPD time. Once the device has entered the Deep Power-down mode, all
instructions are ignored except for the Resume from Deep Power-down command.
Table 12-1. Deep Power-down
Command
Deep Power-down
Serial/8-bit
Both
Opcode
B9H
Figure 12-1. Deep Power-down
CS
SI or IO₇ - IO₀
Opcode
Each transition
represents 8 bits
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