LM3S8971 Datasheet, PDF (5/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
10 General-Purpose Timers ................................................................................................. 201
10.1 Block Diagram ........................................................................................................................ 202
10.2 Functional Description ............................................................................................................. 202
10.2.1 GPTM Reset Conditions .......................................................................................................... 202
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 202
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 204
10.3 Initialization and Configuration ................................................................................................. 208
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 208
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 209
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 209
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 210
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 210
10.3.6 16-Bit PWM Mode ................................................................................................................... 211
10.4 Register Map .......................................................................................................................... 211
10.5 Register Descriptions .............................................................................................................. 212
11 Watchdog Timer ............................................................................................................... 237
11.1 Block Diagram ........................................................................................................................ 237
11.2 Functional Description ............................................................................................................. 237
11.3 Initialization and Configuration ................................................................................................. 238
11.4 Register Map .......................................................................................................................... 238
11.5 Register Descriptions .............................................................................................................. 239
12 Analog-to-Digital Converter (ADC) ................................................................................. 260
12.1 Block Diagram ........................................................................................................................ 261
12.2 Functional Description ............................................................................................................. 261
12.2.1 Sample Sequencers ................................................................................................................ 261
12.2.2 Module Control ........................................................................................................................ 262
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 263
12.2.4 Analog-to-Digital Converter ...................................................................................................... 263
12.2.5 Test Modes ............................................................................................................................. 263
12.2.6 Internal Temperature Sensor .................................................................................................... 263
12.3 Initialization and Configuration ................................................................................................. 264
12.3.1 Module Initialization ................................................................................................................. 264
12.3.2 Sample Sequencer Configuration ............................................................................................. 264
12.4 Register Map .......................................................................................................................... 265
12.5 Register Descriptions .............................................................................................................. 266
13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 293
13.1 Block Diagram ........................................................................................................................ 294
13.2 Functional Description ............................................................................................................. 294
13.2.1 Transmit/Receive Logic ........................................................................................................... 294
13.2.2 Baud-Rate Generation ............................................................................................................. 295
13.2.3 Data Transmission .................................................................................................................. 296
13.2.4 Serial IR (SIR) ......................................................................................................................... 296
13.2.5 FIFO Operation ....................................................................................................................... 297
13.2.6 Interrupts ................................................................................................................................ 297
13.2.7 Loopback Operation ................................................................................................................ 298
13.2.8 IrDA SIR block ........................................................................................................................ 298
13.3 Initialization and Configuration ................................................................................................. 298
13.4 Register Map .......................................................................................................................... 299
October 01, 2007
5
Preliminary