LM3S8971 Datasheet, PDF (43/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
3 Memory Map
The memory map for the LM3S8971 controller is provided in Table 3-1 on page 43.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 43, addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.C000
Peripherals
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x4002.8000
0x4002.C000
0x4003.0000
0x4003.1000
0x4003.2000
0x4003.3000
0x4003.8000
0x4003.C000
0x4004.0000
0x4004.8000
0x400F.C000
0x400F.D000
0x0003.FFFF
0x2000.FFFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.CFFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
0x4002.8FFF
0x4002.CFFF
0x4003.0FFF
0x4003.1FFF
0x4003.2FFF
0x4003.3FFF
0x4003.8FFF
0x4003.CFFF
0x4004.0FFF
0x4004.8FFF
0x400F.CFFF
0x400F.DFFF
Description
On-chip flash ^b
Bit-banded on-chip SRAM^c
Reserved non-bit-banded SRAM space
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved non-bit-banded SRAM space
Watchdog timer
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SSI0
UART0
GPIO Port E
GPIO Port F
GPIO Port G
GPIO Port H
PWM
QEI0
Timer0
Timer1
Timer2
Timer3
ADC
Analog Comparators
CAN0 Controller
Ethernet Controller
Hibernation Module
Flash control
For details on
registers, see
page ...
140
140
-
136
-
239
166
166
166
166
345
300
166
166
166
166
474
507
212
212
212
212
266
456
384
420
123
140
October 01, 2007
43
Preliminary