LM3S8971 Datasheet, PDF (351/577 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S8971 Microcontroller
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BSY
RFF
RNE
TNF
TFE
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bit/Field
31:5
4
Name
reserved
BSY
Type
RO
RO
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
The BSY values are defined as follows:
Value Description
0 SSI is idle.
1 SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
3
RFF
RO
0
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
0 Receive FIFO is not full.
1 Receive FIFO is full.
2
RNE
RO
0
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0 Receive FIFO is empty.
1 Receive FIFO is not empty.
1
TNF
RO
1
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0 Transmit FIFO is full.
1 Transmit FIFO is not full.
October 01, 2007
351
Preliminary