ICS932S801AFLF Datasheet, PDF (5/20 Pages) List of Unclassifed Manufacturers – K8 Clock Chip for Serverworks GC-HT 2-Way Servers

ICS932S801
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +3.8 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage
V_IH
3.3 V +/-5%
2
V_DD + 0.3 V
1
Input Low Voltage
V_IL
3.3 V +/-5%
V_SS - 0.3
0.8
V
1
Input High Current
Input Low Current
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
-5
I_IL2 V_IN = 0 V; Inputs with pull-up resistors -200
5
uA
1
uA
1
uA
1
Operating Current
I_DD3.3OP
all outputs driven
325 mA
Powerdown Current
Input Frequency³
I_DD3.3PD
F_i
V_DD = 3.3 V
100 mA
14.31818
MHz 3
Pin Inductance¹
L_pin
7
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
1
6
pF
1
C_INX
X1 & X2 pins
5
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-assertion of
PD# to 1st clock
3
ms 1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
SMBus Voltage
V_DD
2.7
5.5
V
1
Low-level Output Voltage
V_OL
@ I_PULLUP
0.4
V
1
Current sinking at V_OL = 0.4 V I_PULLUP
4
mA
1
SCLK/SDATA
Clock/Data Rise Time³
T_RI2C (Max VIL - 0.15) to (Min VIH + 0.15)
1000 ns
1
SCLK/SDATA
Clock/Data Fall Time³
T_FI2C (Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet}
ppm frequency accuracy on PLL outputs.
0959C—03/13/06
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