ICS932S801AFLF Datasheet, PDF (15/20 Pages) List of Unclassifed Manufacturers – K8 Clock Chip for Serverworks GC-HT 2-Way Servers

ICS932S801
SMBus Table: SRC Frequency Control Register
Byte 15 Pin #
Name
Control Function Type
0
1
PWD
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
N Divider Prog bit 8 RW _{The decimal representation} X
N Divider Prog bit 9 RW _{of M and N Divier in Byte} X
RW _{15 and 16 will configure}
X
RW _{the SRC VCO frequency.} X
M Divider Programming
bits
RW
RW
RW
Default at power up = latch-
in or Byte 0 Rom table.
VCO Frequency = 14.318
X
X
X
Bit 0
-
M Div0
RW
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
SMBus Table: SRC Frequency Control Register
Byte 16 Pin #
Name
Control Function
Bit 7
-
N Div7
Bit 6
-
N Div6
Bit 5
-
N Div5
Bit 4
-
Bit 3
-
Bit 2
-
N Div4
N Div3
N Div2
N Divider Programming
b(7:0)
Bit 1
-
N Div1
Bit 0
-
N Div0
Type
0
1
RW The decimal representation
RW of M and N Divier in Byte
RW 15 and 16 will configure
RW the SRC VCO frequency.
RW Default at power up = latch-
RW in or Byte 0 Rom table.
RW VCO Frequency = 14.318
x [NDiv(9:0)+8] /
RW
[MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 17 Pin #
Name
Control Function
Bit 7
-
SSP7
Bit 6
-
SSP6
Bit 5
-
SSP5
Bit 4
-
SSP4
Spread Spectrum
Bit 3
-
SSP3
Programming b(7:0)
Bit 2
-
SSP2
Bit 1
-
SSP1
Bit 0
-
SSP0
Type
0
1
RW
RW
RW These Spread Spectrum
RW bits in Byte 17 and 18 will
RW
program the spread
RW
pecentage of SRC
RW
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 18 Pin #
Name
Control Function
Bit 7
-
Reserved
Reserved
Bit 6
-
SSP14
Bit 5
-
SSP13
Bit 4
-
Bit 3
-
Bit 2
-
SSP12
SSP11
SSP10
Spread Spectrum
Programming b(14:8)
Bit 1
-
SSP9
Bit 0
-
SSP8
Type
0
1
R
-
-
RW
RW _{These Spread Spectrum}
RW
RW
RW
bits in Byte 17 and 18 will
program the spread
pecentage of SRC
RW
RW
PWD
0
X
X
X
X
X
X
X
0959C—03/13/06
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